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MRF89XA
FIGURE 3-19:
DATA (NRZ)
DCLK
RX PROCESSING IN CONTINUOUS MODE
Note:
3.9.3
In Continuous mode, it is always recom-
mended to enable the bit synchronizer to
clean the DATA signal even if the DCLK
signal is not used by the Microcontroller
(bit synchronizer is automatically enabled
in Buffered and Packet mode).
INTERRUPT SIGNALS MAPPING
The following table give the description of the interrupts
available in Continuous mode.
TABLE 3-5:
INTERRUPT MAPPING IN CONTINUOUS RX MODE
Interrupt Name
Interrupts
Data Mode
Interrupt Type
Interrupt Source
IRQ0RXS<1:0>
00 (default)
01
10
11
IRQ0
IRQ0
IRQ0
IRQ0
Continuous
Continuous
Continuous
Continuous
Output
Output
Output
Output
Sync Pattern
RSSI
–
–
IRQ1RXS<1:0>
00 (default)
01
10
11
IRQ1
IRQ1
IRQ1
IRQ1
Continuous
Continuous
Continuous
Continuous
Output
Output
Output
Output
DCLK
DCLK
DCLK
DCLK
Note 1:
2:
In Continuous mode, no interrupt is available in Stand-by mode.
See also the DMODE1:DMODE0 bits in the FTXRXIREG and FTPRIREG registers.
TABLE 3-6:
INTERRUPT MAPPING IN CONTINUOUS TX MODE
Interrupt Name
Interrupts
Data Mode
Interrupt Type
Interrupt Source
IRQ0TXST
0 (default)
1
IRQ0
IRQ0
Continuous
Continuous
Output
Output
–
–
IRQ1TX
0 (default)
1
IRQ1
IRQ1
Continuous
Continuous
Output
Output
DCLK
DCLK
Note 1:
2:
In Continuous mode, no interrupt is available in Stand-by mode.
Also refer the DMODE1:DMODE0 bits in the FTXRXIREG and FTPRIREG registers for details.
? 2010–2011 Microchip Technology Inc.
Preliminary
DS70622C-page 75
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